Semiconductor device

ABSTRACT

An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent ApplicationNo. 2015-145180 filed on Jul. 22, 2015, the content of which is herebyincorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and can besuitably utilized, for example, for a semiconductor device including asilicon interposer (simply referred to as an interposer, hereinafter)for integrating a plurality of identical large scale integration (LSI)circuits in which silicon photonics optical waveguides serve asinput/output wires.

BACKGROUND OF THE INVENTION

A technique in which each functional block is mounted for each normalblock in which an integrated circuit device is standardized by a fixedarea is described in Japanese Patent Application Laid-Open PublicationNo. 2003-23090 (Patent Document 1).

Also, a technique in which an additional pattern in a triangular shapeis formed on an end portion of a wiring pattern in a connection marginfor stitching exposure is disclosed in Japanese Patent ApplicationLaid-Open Publication No. H11-67639 (Patent Document 2).

Further, a technique of manufacturing an integrated circuit in which adividing process from a large chip into a plurality of sub chips isparticularly creatively designed so that a common mask can be usedbetween the plurality of sub chips in most steps and a mask for a fewsteps only is separately prepared is disclosed in Japanese PatentApplication Laid-Open Publication No. H5-47622 (Patent Document 3).

SUMMARY OF THE INVENTION

An interposer needs a large plane area in order to mount a plurality ofchips. Since a silicon semiconductor process is used in siliconphotonics, a region may be subjected to dividing to the extent thatpatterning can be performed by photomask depending on a plane area, insome cases. However, in the divided exposure, when an overlay shift ofexposure masks due to an error of overlay accuracy of exposure masks isgenerated in boundary portions to be divided, small irregularities areformed on the surface of the silicon waveguide, and light is scattered,thereby generating a light propagation loss in the silicon waveguides.As a result, there is a need to eliminate an adverse effect caused bythe overlay shift of exposure masks.

The other problems and novel characteristics of the present inventionwill be apparent from the description of the present specification andthe accompanying drawings.

A semiconductor device according to one embodiment includes aninterposer having a quadrangular planar shape, the interposer includes aplurality of identical functional blocks arranged in a first direction,and the functional blocks include a first region in which an electricdevice is arranged, a second region in which an optical device isarranged, and a plurality of optical waveguides. Also, the second regionis arranged between the first region and a first side along the firstdirection of the interposer, and the plurality of optical waveguides arearranged between the second region and the first side and extend fromthe second region toward the first side.

According to one embodiment, a semiconductor device including aninterposer which does not generate degradation of optical propagationcharacteristics in the silicon waveguides can be provided.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1A is a plan view illustrating an essential part of a functionalblock constituting an interposer according to a first embodiment, andFIG. 1B is a plan view illustrating an essential part of the interposer;

FIG. 2 is a cross-sectional view illustrating an essential part of theinterposer in which a cross section taken along a line A1-A1 in FIG. 1Band a cross section taken along a line A2-A2 in FIG. 1B are depicted incombination;

FIG. 3A is a plan view illustrating an essential part of a functionalblock constituting a semiconductor device according to the firstembodiment, and FIG. 3B is a plan view illustrating an essential part ofthe semiconductor device;

FIG. 4 is a cross-sectional view illustrating an essential part of thesemiconductor device in which a cross section taken along a line B1-B1in FIG. 3B and a cross section taken along a line B2-B2 in FIG. 3B aredepicted in combination;

FIG. 5A is a plan view illustrating an essential part of a semiconductordevice of a first modification example according to the firstembodiment, and FIG. 5B is a plan view illustrating an essential part ofa semiconductor device of a second modification example;

FIG. 6 is a schematic view describing a first connection method to anexternal optical system according to the first embodiment;

FIG. 7 is a schematic view describing a second connection method to anexternal optical system according to the first embodiment;

FIG. 8 is a pattern diagram illustrating the semiconductor devices inwhich silicon waveguides are connected to optical fibers by usinggrating couplers according to the first embodiment;

FIG. 9 is a pattern diagram illustrating the semiconductor devices inwhich silicon waveguides are connected to optical fibers by using spotsize converters according to the first embodiment;

FIG. 10 is a conceptional view illustrating a server cluster accordingto the first embodiment;

FIG. 11 is a plan view illustrating an essential part of a semiconductordevice according to a second embodiment; and

FIG. 12 is a plan view illustrating an essential part of a semiconductordevice which is compared and examined by the inventors of the presentinvention.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the entireor a part of the other as a modification example, details, or asupplementary explanation thereof.

Also, in the embodiments described below, when referring to the numberof elements (including number of pieces, values, amount, range, and thelike), the number of the elements is not limited to a specific numberunless otherwise stated or except the case where the number isapparently limited to a specific number in principle. The number largeror smaller than the specified number is also applicable.

Further, in the embodiments described below, it goes without saying thatthe components (including element steps) are not always indispensableunless otherwise stated or except the case where the components areapparently indispensable in principle.

It is also obvious that expressions “composed of A,” “made up of A,”“having A,” and “including A” do not exclude elements other than anelement A, except a case where these expressions are defined asexpressions that refer exclusively to the sole element A. Similarly, inthe embodiments described below, when the shape of the components,positional relation thereof, and the like are mentioned, thesubstantially approximate and similar shapes and the like are includedtherein unless otherwise stated or except the case where it isconceivable that they are apparently excluded in principle. The samegoes for the numerical value and the range described above.

Also, components having the same function are denoted by the samereference symbols throughout the drawings for describing theembodiments, and the repetitive description thereof is omitted. Also, insome drawings used in the embodiments, hatching is used for a siliconwaveguide even in a plan view so as to make the drawings easy to see.Hereinafter, the embodiments of the present invention will be describedin detail based on the drawings.

First, since it is considered that a semiconductor device according toan embodiment will be made clearer, the problem to be solved in aninterposer which constitutes the semiconductor device found by theinventors of the present invention will be described in detail.

An interposer is a relaying substrate which connects substrates eachhaving a different distance between terminals from one another andreferred to as a wiring pitch conversion substrate. The interposerperforms a conversion of a wiring pitch via a wiring board, for example,a build-up board and a thick film board, which facilitates high densitywiring. However, when operating frequency of a system is also set to behigher as signal transmission amount dramatically increases, there is alimitation in an electrical wiring connection.

In recent years, a technique of realizing an optical communicationmodule is achieved by manufacturing a transmission line for an opticalsignal made of silicon and using an optical circuit constituted by thistransmission line for an optical signal as a platform to integrate avariety of optical devices and electronic devices, that is, a siliconphotonics technique has been actively developed.

Compared to the case in which an electrical wire is used like a printedwiring board, use of a silicon waveguide as an optical wire considerablyeliminates a bottleneck of transmission delay, thereby enabling ahigh-speed data transfer.

FIG. 12 is a plan view illustrating an essential part of a semiconductordevice which is compared and examined by the inventors of the presentinvention.

In FIG. 12, a multi-core in which four identical semiconductor chips SCare arranged in two rows×two columns on a main surface of an interposerIP0 is formed. Further, a single light emitting element (laser diode)chip LDC and a single light receiving element (photodiode) chip PDC aredisposed adjacent to a single semiconductor chip SC.

The semiconductor chip SC and a power supply potential or a groundpotential, the semiconductor chip SC and the light emitting element chipLDC, and the semiconductor chip SC and the light receiving element chipPDC are electrically connected by an electric wire ML made of aconductive material formed on the main surface of the interposer IP0.Meanwhile, an optical fiber, for example, is used for output of anoptical signal from the light emitting element chip LDC and input of anoptical signal to the light receiving element chip PDC, and the opticalfiber is connected to the light emitting element chip LDC or the lightreceiving element chip PDC by a silicon waveguide PC.

However, as illustrated in FIG. 12, when one ends of the siliconwaveguides PC to connect the optical fiber are collected at one side ofthe interposer IP0, at least two sheets of exposure masks each having adifferent pattern layout (an exposure mask for an upper region of thepaper and an exposure mask for a lower region of the paper) are requiredin forming the silicon waveguide PC so as to expose a single siliconwaveguide PC without dividing. Further, in the case where an area of asingle semiconductor chip SC is large or the number of the semiconductorchips SC increases, the area of the interposer IP0 also increases,thereby requiring four or more sheets of exposure masks having patternlayouts different from one another.

In addition, in the layout of the silicon waveguide PC illustrated inFIG. 12, in forming the silicon waveguide PC by using four sheets ofexposure masks, some silicon waveguides PC are formed by dividedexposure. Use of the divided exposure generates an overlay shift of theexposure mask due to an error of overlay accuracy of the exposure maskin the boundary portion to be divided. When small irregularities due tothe overlay shift of the exposure mask are formed on the surface of thesilicon waveguide PC, light is scattered, resulting in a lightpropagation loss of the silicon waveguide PC. Since a singulardimensional change in the silicon waveguide PC leads to degradation oflight propagation characteristics, even if an auxiliary pattern isadded, it is not an essential solution to the light propagation loss.

Although collecting the electric wires ML has also been examined, theelectric wires ML get longer, thereby generating a problem such as delayof an electric signal.

In addition, although a chemically amplified resist may be used in anexposure technique requiring fine processing, the chemically amplifiedresist changes with time, so that management of a process time isrequired. In particular, when a plurality of exposure masks,specifically three or more sheets of exposure masks are switched toexpose, management of a process time becomes extremely difficult. Changewith time in the chemically amplified resist can be a cause of degradingprocessing accuracy of the silicon waveguide PC, as well as a mechanicalalignment shift of an exposure apparatus.

First Embodiment

A configuration of a semiconductor device according to a firstembodiment will be described with reference to FIGS. 1 and 2. FIG. 1A isa plan view illustrating an essential part of a functional blockconstituting an interposer according to the first embodiment, and FIG.1B is a plan view illustrating an essential part of the interposer, eachindicating a plan view illustrating an essential part seen through aprotective film, an interlayer dielectric film, and the like on asubstrate. FIG. 2 is a cross-sectional view illustrating an essentialpart of the interposer in which a cross section taken along a line A1-A1in FIG. 1B and a cross section taken along a line A2-A2 in FIG. 1B aredepicted in combination.

As illustrated in FIGS. 1 and 2, a planar shape of an interposer IP1which intersects with its thickness direction has a quadrangular shape,and sides along with an x direction are long sides while sides alongwith a y direction are short sides. The interposer IP1 has insulatingfilms CL1 and CL2 on an upper surface and a lower surface of a substrateSB made of single-crystal silicon (Si), respectively, and a plurality ofsilicon waveguides PC made of silicon (Si) formed via the insulatingfilm CL1 (also referred to as a BOX layer and a lower cladding layer)formed on the upper surface. Further, the interposer IP1 has aninterlayer dielectric film IL (also referred to as an upper claddinglayer) formed to cover the plurality of silicon waveguides PC, aplurality of electric wires ML formed on the interlayer dielectric filmIL and made of a conductive material, and a protective film PL formed tocover the plurality of electric wires ML. An opening CT is formed in apart of the protective film PL, and a part of the electric wire ML isexposed on the bottom surface of the opening CT.

The interposer IP1 has a plurality of identical functional blocks MDarranged in the x direction, for example, and the functional blocks MDinclude a first region R1 in which a semiconductor chip is arranged, asecond region R2 in which a light emitting element chip is arranged, anda third region R3 in which alight receiving element chip is arranged.Then, the second region R2 in which a light emitting element chip isarranged and the third region R3 in which a light receiving element chipis arranged are provided between the first region R1 in which asemiconductor chip is arranged and one of the long sides along the xdirection of the interposer IP1.

Of the plurality of electric wires ML, power supply/GND lines to beelectrically connected to a power supply potential or a ground potentialextend, for example, in the x direction, and the functional blocks MDadjacent in the x direction are electrically connected to one anothervia the power supply/GND lines, respectively. Further, of the pluralityof electric wires ML, signal lines extend, for example, in the ydirection.

In contrast, all of the plurality of silicon waveguides PC forconnecting to optical fibers, for example, extend in the y direction andare not formed between the functional blocks MD adjacent in the xdirection. More specifically, the plurality of silicon waveguides PCextending in the y direction are arranged between the second region R2in which a light emitting element chip is arranged and one of the longsides along the x direction of the interposer IP1, and between the thirdregion R3 in which a light receiving element chip is arranged and one ofthe long sides along the x direction of the interposer IP1,respectively. That is, the plurality of silicon waveguides PC are notcontinuously formed between the functional blocks MD adjacent in the xdirection and formed to be positioned within a single functional blockMD.

Accordingly, as an exposure mask to be used in forming the siliconwaveguides PC, only one sheet of exposure mask to expose a singlefunctional block MD is required, so that cost for masks can be reducedand time management in an exposure process is facilitated as well.

In addition, since the plurality of silicon waveguides PC are formed tobe positioned within a single functional block MD, exposing a singlefunctional block MD with a sheet of exposure mask eliminates a need touse the divided exposure in forming the silicon waveguides PC. Thus, aproblem that an overlay shift of an exposure mask is generated in thedivided exposure is eliminated, so that a light propagation loss of thesilicon waveguides PC due to the irregularities on the surfaces thereofcan be avoided.

Next, the configuration of the semiconductor device according to thefirst embodiment will be described with reference to FIGS. 3 and 4. FIG.3A is a plan view illustrating an essential part of the functional blockconstituting the semiconductor device according to the first embodiment,and FIG. 3B is a plan view illustrating an essential part of thesemiconductor device, each indicating a plan view illustrating anessential part seen through a sealing resin film, a protective film, aninterlayer dielectric film, and the like on the substrate. FIG. 4 is across-sectional view illustrating an essential part of the semiconductordevice in which a cross section taken along a line B1-B1 in FIG. 3B anda cross section taken along a line B2-B2 in FIG. 3B are depicted incombination.

As illustrated in FIGS. 3 and 4, on the upper surface of the interposerIP1, the semiconductor chip SC, the light emitting element chip LDC, andthe light receiving element chip PDC are in flip-flop connection viaexternal terminals. More specifically, external terminals TE1 of thesemiconductor chips SC are made to be opposed to the electric wires MLof the interposer IP1 and are allowed to connect facedown to theelectric wires ML of the interposer IP1 all at once. Similarly, externalterminals of the light emitting element chips LDC are made to be opposedto the electric wires ML of the interposer IP1 and are allowed toconnect facedown to the electric wires ML of the interposer IP1 all atonce. Similarly, external terminals of the light receiving element chipsPDC are made to be opposed to the electric wires ML of the interposerIP1 and are allowed to connect facedown to the electric wires ML of theinterposer IP1 all at once. Further, though not illustrated, the sealingresin film is formed on the upper surface of the interposer IP1 so as tocover the semiconductor chips SC, the light emitting element chips LDC,and the light receiving element chips PDC. A semiconductor integratedcircuit device, for example, a logic circuit or a memory circuit, isformed in the semiconductor chip.

According to the first embodiment, the light emitting element chip LDCand the light receiving element chip PDC are used as a light emittingelement and a light receiving element, respectively, but are not limitedto this. For example, alight emitting element made of silicon (Si) whichis present in the same layer as silicon (Si) constituting the siliconwaveguides PC may be formed on the upper surface of the substrate SB viaan insulating film CL1. In this case, a control chip for controlling thelight emitting element can be mounted, or a control circuit can beformed on the upper surface of the substrate SB.

Similarly, a light receiving element made of silicon (Si) which ispresent in the same layer as silicon (Si) constituting the siliconwaveguides PC may be formed on the upper surface of the substrate SB viaan insulating film CL1. In this case, a control chip for controlling thelight receiving element can be mounted, or a control circuit can beformed on the upper surface of the substrate SB.

In addition, the arrangement of the semiconductor chip SC, the lightemitting element chip LDC, and the light receiving element chip PDC isnot limited to the arrangement illustrated in FIGS. 3 and 4.Modification examples of the semiconductor device according to the firstembodiment will be described below.

FIG. 5A is a plan view illustrating an essential part of thesemiconductor device of a first modification example according to thefirst embodiment, and FIG. 5B is a plan view illustrating an essentialpart of the semiconductor device of a second modification example.

As illustrated in FIG. 5A, in the interposer IP2, the second region inwhich the light emitting element chip LDC is arranged and the thirdregion in which the light receiving element chip PDC is arranged areprovided on one side of the x direction and on the other side of the xdirection, respectively, with the first region in which thesemiconductor chip SC is arranged sandwiched therebetween, in a singlefunctional block MD. Then, the semiconductor chip SC is mounted in thefirst region, the light emitting element chip LDC is mounted in thesecond region, and the light receiving element chip PDC is mounted inthe third region.

Of the plurality of electric wires ML, power supply/GND lines to beelectrically connected to a power supply potential or a ground potentialextend in the y direction toward one of the long sides along the xdirection of the interposer IP2, for example. Further, of the pluralityof electric wires ML, signal lines extend in the x direction and the ydirection, for example.

In contrast, all of the plurality of silicon waveguides PC forconnecting to the optical fibers, for example, extend in the y directionand are not formed between the functional blocks MD adjacent in the xdirection. More specifically, the plurality of silicon waveguides PCextending in the y direction are arranged between the second region inwhich the light emitting element chip LDC is arranged and the other ofthe long sides along the x direction of the interposer IP2, and betweenthe third region in which the light receiving element chip PDC isarranged and the other of the long sides along the x direction of theinterposer IP2, respectively. That is, the plurality of siliconwaveguides PC are not continuously formed between the functional blocksMD adjacent in the x direction and are formed to be positioned within asingle functional block MD.

In addition, as illustrated in FIG. 5B, in the interposer IP3, thesecond region in which the light emitting element chip LDC is arrangedand the third region in which the light receiving element chip PDC isarranged are provided on one side of the x direction and on the otherside of the x direction, respectively, with the first region in whichthe semiconductor chip SC is arranged sandwiched therebetween, in asingle functional block MD, like the interposer IP2. Then, thesemiconductor chip SC is mounted in the first region, the light emittingelement chip LDC is mounted in the second region, and the lightreceiving element chip PDC is mounted in the third region.

Of the plurality of electric wires ML, power supply/GND lines to beelectrically connected to a power supply potential or a ground potentialextend in the y direction toward one of the long sides along the xdirection of the interposer IP3, for example. Further, of the pluralityof electric wires ML, signal lines extend in the x direction and the ydirection, for example.

In contrast, all of the plurality of silicon waveguides PC forconnecting to the optical fibers, for example, extend in the x directionand are not formed between the functional blocks MD adjacent in the xdirection. More specifically, the plurality of silicon waveguides PCextending in the x direction are arranged between the second region inwhich the light emitting element chip LDC is arranged and one of thesides along the y direction of the functional block MD, and between thethird region in which the light receiving element chip PDC is arrangedand the other of the sides along the y direction of the functional blockMD, respectively. That is, the plurality of silicon waveguides PC arenot continuously formed between the functional blocks MD adjacent in thex direction and are formed to be positioned within a single functionalblock MD.

Accordingly, also in the first and second modification examples, onlyone sheet of exposure mask to be used in forming the silicon waveguidesPC is required, so that cost for masks can be reduced and timemanagement in an exposure process is facilitated as well.

In addition, exposing a single functional block MD with a sheet ofexposure mask eliminates a need to use the divided exposure in formingthe silicon waveguides PC. Thus, a problem that an overlay shift of anexposure mask is generated in the divided exposure is eliminated, sothat a light propagation loss of the silicon waveguides PC due to theirregularities on the surfaces thereof can be avoided.

Next, a method of connecting the semiconductor device to an externaloptical system according to the first embodiment will be described withreference to FIGS. 6 and 7. FIG. 6 is a schematic view describing afirst connection method to the external optical system according to thefirst embodiment. FIG. 7 is a schematic view describing a secondconnection method to the external optical system according to the firstembodiment.

For example, light propagated through the silicon waveguide enters anexternal optical system, for example, an optical fiber. However, whenthe silicon waveguide and the optical fiber are directly connected, alarge coupling loss is generated at the connection portion. Accordingly,it is required to reduce such a coupling loss by using a gratingcoupler, a spot size converter, or the like.

FIG. 6 is a schematic view illustrating a mode in which lightpropagating through the silicon waveguide PC formed in the interposerIP1 enters the optical fiber LF by using the grating coupler.

Light propagated through the silicon waveguide PC is diffracted andradiated in a specified direction in the grating coupler (notillustrated) by periodic refractive-index modulation (the irregularitieson the surface, for example) provided along the propagating direction.Then, this diffracted and radiated light enters the optical fiber LFconnected to the grating coupler.

FIG. 6 illustrates a functional block MD including a semiconductorintegrated circuit LSI constituted by a plurality of semiconductorelements formed on the upper surface of the substrate, a light emittingelement LD formed by using silicon (Si) present on the upper surface ofthe substrate, and a light receiving element PD formed by using silicon(Si) present on the upper surface of the substrate.

FIG. 7 is a schematic view illustrating a mode in which lightpropagating through the silicon waveguide PC formed in the interposerIP1 is output into the optical fiber LF by using the spot sizeconverter.

The spot size converter (not illustrated) makes the spot size of thelight propagated through the silicon waveguide PC approximately as largeas the spot size of the optical fiber LF, and then, the light having theenlarged spot size enters the optical fiber LF. Thus, a coupling losscan be reduced.

FIG. 7 illustrates a functional block MD including a semiconductor chipSC, a light emitting element chip LDC, and a light receiving element PDformed by using silicon (Si) present on the upper surface of thesubstrate.

Next, modes of the plurality of semiconductor devices mounted on aprinted wiring board according to the first embodiment will be describedwith reference to FIGS. 8 and 9. FIG. 8 is a pattern diagramillustrating the semiconductor devices in which the silicon waveguidesare connected to the optical fibers by using the grating couplersaccording to the first embodiment. FIG. 9 is a pattern diagramillustrating the semiconductor devices in which the silicon waveguidesare connected to the optical fibers by using the spot size convertersaccording to the first embodiment.

As illustrated in FIGS. 8 and 9, an interposer IP1 a on which asemiconductor chip SC1 having a logic circuit and the like formedtherein, for example, is mounted, an interposer IP1 b on which asemiconductor chip SC2 having a buffer memory formed therein, forexample, is mounted, ball grid arrays BGAs, and the like are mounted onan upper surface of a printed wiring board MS (referred to also as amounting board or a packaging board). The ball grid array BGA is asemiconductor device in which small ball-shaped external terminals TEmade of solder are arranged in a grid pattern. Arranging thesesemiconductor devices on the upper surface of the printed wiring boardMS can constitute a server, for example. Though not illustrated, a lightemitting element and a light receiving element which are made of silicon(Si) are formed on first main surfaces of the interposers IP1 a and IP1b, respectively.

External terminals TE2 a and TE2 b formed on second main surfaces of theinterposers IP1 a and IP1 b, respectively, are electrically connected toa wiring layer formed on the upper surface of the printed wiring boardMS for supplying power and connecting to some signal wires.

In contrast, a signal can be interactively transmitted between thesemiconductor chip SC1 mounted on the first main surface of theinterposer IP1 a and the semiconductor chip SC2 mounted on the firstmain surface of the interposer IP1 b via the optical fibers LF. Further,a signal is transmitted from the server to the outside via the opticalfiber LF and an optical connector LC. Thus, by using the optical fibersLF, light can be propagated even over a relatively long distance with nopropagation loss without being affected by noise, so that there is anadvantage of increasing the freedom of arranging the interposers IP1 aand IP1 b on the printed wiring board MS.

Next, an example of a server cluster in which a plurality of serversaccording to the first embodiment are connected will be described withreference to FIG. 10. FIG. 10 is a conceptional view illustrating theserver cluster according to the first embodiment. The server clusterindicates a group of independent servers working together as a singlesystem, and a server configuration requiring an I/O connection isillustrated herein. FIG. 10 illustrates the semiconductor devices whichare shown in FIG. 9 and connected to the optical fibers by using thespot size converters, but semiconductor devices are not limited to this.

As illustrated in FIG. 10, a plurality of servers SV mounted on a serverrack SR are connected to an interface which is common to one another viathe optical connectors LC, for example. By operating either one of theplurality of servers SV, high availability can be achieved. In the firstembodiment, since the semiconductor chip SC1 and the semiconductor chipSC2 which constitute each server SV are connected with each other viathe optical fibers LF, and further, each server SV is connected to theinterface via the optical connector LC, a large-capacity transmissionwith an extremely reduced transmission loss over a long distance can beperformed.

Thus, according to the first embodiment, since the divided exposure isnot required in forming the silicon waveguides PC, a problem that anoverlay shift of an exposure mask is generated in the divided exposureis eliminated, thereby avoiding a light propagation loss of the siliconwaveguides PC due to the irregularities on the surfaces thereof.Further, only one sheet of exposure mask to be used in forming thesilicon waveguides PC is required, so that cost for masks can be reducedand time management in an exposure process is facilitated as well.

Note that, in the first embodiment, exposure without requiring thedivided exposure is performed in forming the silicon waveguides PC, andit is also possible to perform exposure without requiring the dividedexposure in forming the electric wires ML and to form the electric wiresML which are not disposed across the divided boundary of the exposuremask.

Second Embodiment

A configuration of a semiconductor device according to a secondembodiment will be described with reference to FIG. 11. FIG. 11 is aplan view illustrating an essential part of an interposer according tothe second embodiment and indicates a plan view illustrating anessential part seen through a protective film and an interlayerdielectric film on a substrate.

As illustrated in FIG. 11, four functional blocks MD are arranged in tworows×two columns on a main surface of an interposer IP5. In theinterposer IP5, a second region in which a light emitting element chipLDC is arranged and a third region in which a light receiving elementchip PDC is arranged are provided between a first region in which asemiconductor chip SC is arranged and either of the sides along the xdirection of the interposer IP5, respectively, in a single functionalblock MD, like the functional block MD of the interposer IP1. Then, thesemiconductor chip SC is mounted in the first region, the light emittingelement chip LDC is mounted in the second region, and the lightreceiving element chip PDC is mounted in the third region.

Further, in the two functional blocks MD adjacent in the y direction,the layout is inverted between the two functional blocks. That is, inthe two functional blocks MD positioned on an upper region of the paper,the second region in which the light emitting element chip LDC isarranged and the third region in which the light receiving element chipPDC is arranged are positioned between the first region in which thesemiconductor chip SC is arranged and one of the sides along the xdirection of the interposer IP5 on the +y direction side. Then, theplurality of waveguides PC are arranged between the second region inwhich the light emitting element chip LDC is arranged and the one of thesides along the x direction of the interposer IP5 on the +y directionside, and between the third region in which the light receiving elementchip PDC is arranged and the one of the sides along the x direction ofthe interposer IP5 on the +y direction side, respectively.

In the two functional blocks MD positioned on a lower region of thepaper, the second region in which the light emitting element chip LDC isarranged and the third region in which the light receiving element chipPDC is arranged are positioned between the first region in which thesemiconductor chip SC is arranged and the other of the sides along the xdirection of the interposer IP5 on the −y direction side. Then, theplurality of silicon waveguides PC are arranged between the secondregion in which the light emitting element chip LDC is arranged and theother of the sides along the x direction of the interposer IP5 on the −ydirection side, and between the third region in which the lightreceiving element chip PDC is arranged and the other of the sides alongthe x direction of the interposer IP5 on the −y direction side,respectively.

Of the plurality of electric wires ML, power supply/GND lines to beelectrically connected to a power supply potential or a ground potentialextend, for example, in the x direction, and the functional blocks MDadjacent in the x direction are electrically connected to one anothervia the power supply/GND lines, respectively. Further, of the pluralityof electric wires ML, signal lines extend, for example, in the ydirection.

In contrast, all of the plurality of silicon waveguides PC forconnecting to the optical fibers, for example, extend in the y directionand are not formed between the functional blocks MD adjacent in the xdirection and between the functional blocks MD adjacent in the ydirection. More specifically, the plurality of silicon waveguides PCextending in the y direction are arranged between the second region inwhich the light emitting element chip LDC is arranged and the one of thesides along the x direction of the interposer IP5, and between the thirdregion in which the light receiving element chip PDC is arranged and theone of the sides along the x direction of the interposer IP5,respectively, or between the second region and the other of the sidesalong the x direction of the interposer IP5, and between the thirdregion and the other of the sides along the x direction of theinterposer IP5, respectively. That is, the plurality of siliconwaveguides PC are not continuously formed between the functional blocksMD adjacent in the x direction or in the y direction and are formed tobe positioned within a single functional block MD.

Accordingly, exposing a single functional block MD with a sheet ofexposure mask eliminates a need to use the divided exposure in formingthe silicon waveguides PC. Thus, a problem that an overlay shift of anexposure mask is generated in the divided exposure is eliminated, sothat a light propagation loss of the silicon waveguides PC due to theirregularities on the surfaces thereof can be avoided.

However, in the second embodiment, since the layouts of the twofunctional blocks MD adjacent in the y direction are different from eachother, two sheets of exposure masks (an exposure mask for the upperregion of the paper and an exposure mask for the lower region of thepaper) are required in forming the silicon waveguides PC. Accordingly,it is effective for an exposure apparatus having a switching function oftwo sheets of exposure masks in one exposure process. In addition, inthe second embodiment, when the two functional blocks MD adjacent in they direction can be exposed all at once, only one sheet of exposure maskto be used in forming the silicon waveguides PC is required, so thatcost for masks can be reduced and time management in an exposure processis facilitated as well.

Thus, according to the second embodiment, since the divided exposure isnot required in forming the silicon waveguides PC, a problem that anoverlay shift of an exposure mask is generated in the divided exposureis eliminated, thereby avoiding a light propagation loss of the siliconwaveguides PC due to the irregularities on the surfaces thereof.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

1-10. (canceled)
 11. A semiconductor device comprising: an interposerhaving a quadrangular planar shape including first and second sidesalong a first direction and third and fourth sides along a seconddirection being perpendicular to the first direction, wherein theinterposer includes a first functional block and a second functionalblock being adjacent to the first function block in the seconddirection, wherein each of the first and second functional blocksincludes a first region in which an electric device is arranged, asecond region in which an optical device is arranged, and a plurality ofoptical waveguides, wherein the second region of the first functionalblock is arranged between the first region of the first functional blockand the first side, wherein the optical waveguides of the firstfunctional block are arranged between the second region of the firstfunctional block and the first side, and extend from the second regionof the first functional block to the first side, wherein the secondregion of the second functional block is arranged between the firstregion of the second functional block and the second side, and whereinthe optical waveguides of the second functional block are arrangedbetween the second region of the second functional block and the secondside, and extend from the second region of the second functional blockto the second side.
 12. The semiconductor device according to claim 11,wherein the interposer includes: a substrate made of silicon; a firstinsulating film formed on an upper surface of the substrate; the opticalwaveguides made of silicon and formed on the first insulating film; asecond insulating film formed to cover the optical waveguides; and aplurality of electric wires formed on the second insulating film. 13.The semiconductor device according to claim 12, wherein the interposerfurther includes a third functional block being adjacent to the firstfunctional block in the first direction, and wherein a power supplypotential wire or a ground potential wire of the electric wires extendin the first direction so as to be arranged between the first functionalblock and the third functional block.
 14. The semiconductor deviceaccording to claim 11, wherein, for one of the first and secondfunctional blocks, the optical device is made of silicon that is presentin a same layer as silicon constituting the plurality of opticalwaveguides.
 15. The semiconductor device according to claim 11, whereinthe optical waveguides of the first and second functional blocks do notextend in the second direction.